This invention relates to phase locked loops, and more specifically, to phase locked loop circuitry which will not lock when the voltage controlled oscillator (VCO) of the phase locked loop produces a signal which has a frequency that is a harmonic of the frequency of input signal. For purposes of this specification, the term "harmonic" includes harmonics, which are integral multiples of a frequency, and sub-harmonics, which are integral fractions of a frequency.
An example of a prior art phase locked loop is shown in FIG. 1. Phase locked loop 6 is designed to "lock" with the signal V.sub.in placed on input terminal 5. Phase locked loop 6 is "locked" when the frequency of the output signal V.sub.out on output lead 2 of VCO 1 is equal to the frequency of the input signal on input terminal 5. VCO 1 varies the frequency of the output signal on output lead 2 linearly with the voltage signal applied to input lead 3. Output lead 2 of VCO 1 is connected to one input lead of Exclusive-OR gate 4. The other input lead of Exclusive-OR gate 4 is connected to input terminal 5 for receiving an input signal V.sub.in. The output lead of Exclusive-OR gate 4 is connected to the input lead of integrator 7. Exclusive-OR gate 4 provides an output signal on its output lead which, when integrated by integrator 7, is proportional to the phase difference between the output signal of VCO 1 and the input signal received on input terminal 5. When phase locked loop 6 is locked, this output signal is nearly a constant voltage. The output lead of integrator 7 is connected to input lead 3 of voltage controlled oscillator 1. Output lead 10 provides to external circuitry (not shown) a voltage signal having a voltage which is proportional to the frequency of the input signal provided on input lead 5. Thus, phase locked loop 6 may be used as a frequency modulation demodulator by applying an F.M. signal to input lead 5, and receiving the demodulated signal on lead 10.
FIG. 2 is a diagram of a phase locked loop 17 which is adapted for use as a frequency multiplier. Frequency divider 13 provides an output signal to Exclusive-OR gate 4 which is the result of dividing the output signal from VCO 1 by a selected integer. Exclusive-OR gate 4 compares the output signal from frequency divider 13 with the input signal applied to input lead 5. Therefore, when phase locked loop 17 is locked with input signal V.sub.in, the output signal of VCO 1 has a frequency which is an integral multiple of the frequency of input signal V.sub.in.
FIGS. 3a through 3d depict an example of the voltage versus time graphs for the voltage at terminals 5, 2, 11 and 3 respectively of FIG. 1, when the input signal on input lead 5 has a frequency within the lower one-fourth of the frequency range of VCO 1. For simplicity of discussion, as shown in FIG. 3a, the input signal on input terminal 5 is a squarewave although, regardless of the type of the input signal to Exclusive-OR gate 4, (i.e., squarewave, sinewave, ramp, etc.) the output signals of VCO 1 and Exclusive-OR gate 4 are squarewaves.
In this example, the input signal applied to input lead 3 of VCO 1 has a voltage range of 0 to 5 volts. Of importance, because the frequency of the input signal is low, the phase difference .phi. between the input signal on lead 5 and the output signal of VCO 1 on output lead 2 is small (less than 45.degree.). The output signal on output lead 11 of Exclusive-OR gate 4 is shown in FIG. 3c. The output waveform of integrator 7 is shown in FIG. 3d. An ideal integrator produces the time weighted sum of the voltages applied to the integrator. Therefore, if integrator 7 were an ideal integrator, the output signal provided on output lead 3 would be represented by the dotted line shown in FIG. 3d. However, in reality, the output signal of integrator 7 includes components of the input signal to integrator 7. The waveform shown in FIG. 3d has exaggerated swings of amplitude to illustrate the relationship between the waveforms in FIG. 3c and FIG. 3d. In practice, these components of input signal V.sub.in on the output signal from integrator 7 are small and thus inconsequential. The output signal of integrator 7 is within the range of approximately 0 to 1.25 volts, thus causing VCO 1 to produce an output signal having the frequency necessary for phase locked loop 6 to lock with the low frequency input signal V.sub.in.
FIGS. 4a through 4d are time versus voltage diagrams of the voltages on leads 5, 2, 11 and 3 of FIG. 1, respectively, when the frequency of the input signal on input lead 5 is in the upper one-fourth of the frequency range of VCO 1. Of importance, when phase locked loop 1 is locked on a signal having a frequency close to the maximum frequency of VCO 1, the phase difference .phi. between the waveforms on leads 5 and 2 is large (greater than approximately 135.degree.). The output signal on output lead 11 of Exclusive-OR gate 4 is shown in FIG. 4c. The output signal of integrator 7 is shown in FIG. 4d. The voltage swings of the waveform shown in FIG. 4d are exaggerated to illustrate the relationship between the waveform in FIG. 4d and the waveform in FIG. 4c. Of importance, the voltage value of the signal in FIG. 4d is within the range of approximately 3.75 to 5 volts, thus causing VCO 1 to provide the high frequency output signal on lead 2 necessary for phase locked loop 6 to lock with the high frequency of the input signal on input lead 5. The relationship between the voltage provided on input lead 3 of VCO 1 and the phase difference .phi. between the waveforms on leads 2 and 5 is shown in FIG. 5.
One problem with phase locked loops employing Exclusive-OR gate phase detectors is that these phase locked loops will lock when VCO 1 provides an output signal having a frequency which is a harmonic of the frequency of the input signal on input lead 5. This phenomenon is illustrated in FIGS. 6a thorugh 6g. FIGS. 6a through 6g are the voltage versus time waveforms on leads 2, 5, 11 and 3 of FIG. 1. In this example, two frequencies which may cause VCO 1 to produce the signal provided on lead 2 (shown in FIG. 6a) are shown in FIGS. 6b and 6c. The signal produced by VCO 1 and placed on lead 2 is shown in FIG. 6a. The signal on FIG. 6a has a frequency which is one-half the frequency of the signal in FIG. 6c. In this example the input voltage applied to input lead 3 of VCO 1 necessary to produce a signal of the frequency shown in FIG. 6a is approximately 2.5 volts. The output signal provided on output lead 11 of Exclusive-OR gate 4 when Exclusive-OR gate 4 combines the waveforms in FIGS. 6a and 6b is shown in FIG. 6d. The signal in FIG. 6d is integrated by integrator 7 to provide the waveform in FIG. 6f. The waveform of FIG. 6f provides the voltage to input lead 3 of VCO 1 necessary to produce the signal of FIG. 6a.
The output signal provided on output lead 11 of Exclusive-OR gate 4 when Exclusive-OR gate 4 combines waveforms 6a and 6c is shown in FIG. 6e. The output signal provided by integrator 7 when the waveform in FIG. 6e is the input signal to integrator 7 is shown in FIG. 6g. Of importance, the signal shown in FIG. 6a provides the voltage to input lead 3 of VCO 1 necessary to produce the waveform shown in FIG. 6a, even though the frequency of the signal shown in FIG. 6c is twice the frequency of the signal shown in FIG. 6a. Therefore, phase locked loop 6 properly locks with the input signal shown in FIG. 6b, and yet may improperly lock with the input signal shown in FIG. 6c. The phase locked loop shown in FIG. 1 and the phase locked loop shown in FIG. 2 may incorrectly lock by providing an output signal which is a harmonic of the frequency of input signal V.sub.in provided on input lead 5. This harmonic locking problem may be solved by using an edge triggered phase detector as is used in RCA part number CD 4046A. However, phase locked loops using an edge triggered phase detector are very sensitive to noise in that noise spikes in the input signal will "unlock" the phase locked loop. Accordingly, it is desirable to have a phase locked loop which does not use an edge triggered phase detector which will not lock on harmonic frequencies of the input signal to be locked.